The ProductThe CacheQ Ultravisor Flow
The QCC development platform accepts HLL (C source or object) as input and through a number of steps generates an optimized partitioned accelerated executable. The output is an x86 executable and a file that is loaded into an FPGA.
The CacheQ Virtual Machine
The CacheQ Virtual Machine is a complete software representation of the application. It supports design analysis, profiling, performance simulation and application partitioning. It enables high bandwidth memory integration. All across multiple platforms.
THe Development Flow
The development flow takes HLL, generates a CQVM, performs optimization and partitioning and then generates an x86 executable and system Verilog. The system Verilog is processed by FPGA tools to generate a “bitstream”. Even though the system produces RTL the RTL is a representation of the fully pipelined CQVM and not state machine controlled digital logic. The CQVM also supports user-guided partitioning, performance simulation, profiling, memory configuration (size and stripping) and resource estimates. Minor modifications are usually implemented to enhance the performance of the application. These changes can be fully validated in a standard SW development environment.